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-- Project		: ECE 251 FINAL PROJECT
-- Author 		: Mahmut Yilmaz
-- Last Modified: 05/01/2007
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.all;

ENTITY packetgen_all IS
	PORT (	clock			: IN  STD_LOGIC;	-- PosEdge Clock used	
			enable			: IN  STD_LOGIC;	
			start			: IN  STD_LOGIC;	
			N				: IN  STD_LOGIC_VECTOR(15 DOWNTO 0); 			
      		random_out		: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) 	-- output pseudo-random number & CRC
			);
END packetgen_all;

ARCHITECTURE struct OF packetgen_all IS
	COMPONENT packetgen_8 IS
		PORT (	clock_eth		: IN  STD_LOGIC;	-- PosEdge Clock used	
				clock_crc		: IN  STD_LOGIC;	-- PosEdge Clock used
				enable			: IN  STD_LOGIC;	
				start			: IN  STD_LOGIC;	
				N				: IN  STD_LOGIC_VECTOR(15 DOWNTO 0); 			
	      		random_out		: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) 	-- output pseudo-random number & CRC
				);
	END COMPONENT;
	
	COMPONENT N_delay IS
		PORT (	clock			: IN  STD_LOGIC;	-- PosEdge Clock used	
				input			: IN  STD_LOGIC_VECTOR (3 DOWNTO 0);	-- Flop input
	      		q	 			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) 	-- Flop output
				);
	END COMPONENT;
	
	COMPONENT counter_8 IS
		PORT(	clock	:	IN std_logic;
				clear	:	IN std_logic;
				count	:	IN std_logic;
				q		:	OUT std_logic_vector(7 DOWNTO 0)
		);
	END COMPONENT;
	
	COMPONENT add_packet_header IS
		PORT (	clock			: IN  STD_LOGIC;	-- PosEdge Clock used	
				start			: IN  STD_LOGIC;	-- Resets the flop to 0, active HIGH
				N				: IN  STD_LOGIC_VECTOR (15 DOWNTO 0) ;	-- Flop input
	      		q	 			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) 	-- Flop output
				);
	END COMPONENT;

	COMPONENT mux21 IS
		PORT (	in0,in1			: IN  STD_LOGIC_VECTOR (3 DOWNTO 0);	-- Multiplexer inputs	
				sel				: IN  STD_LOGIC;	-- Multiplexer select
	      		q_m	 			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) 	-- Multiplexer output
				);
	END COMPONENT;
	
	COMPONENT simple_comparator_8 IS
		PORT (	in0	: IN  STD_LOGIC_VECTOR (7 DOWNTO 0);
	      		q	: OUT STD_LOGIC
				);
	END COMPONENT;
	
	COMPONENT clock_freq_divider IS
		PORT (	clock_in_50MHz : IN  STD_LOGIC;
				clock_out_25MHz: OUT  STD_LOGIC;
				clock_out_12_5MHz: OUT  STD_LOGIC
				);
	END COMPONENT;
	
	SIGNAL counter_out:STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL pre_random_out, pre_mux_out,header_out: STD_LOGIC_VECTOR (3 DOWNTO 0);
	SIGNAL mux_select,clock_eth,clock_crc: STD_LOGIC;
BEGIN

	xclock_freq_divider: clock_freq_divider PORT MAP (clock_in_50MHz=>clock,clock_out_25MHz=>clock_eth,
				clock_out_12_5MHz=>clock_crc);
	xpacketgen_8: packetgen_8 PORT MAP (clock_eth=>clock_eth,clock_crc=>clock_crc,enable=>enable,start=>start,
				N=>N,random_out=>pre_random_out);
	xN_delay: N_delay PORT MAP (clock=>clock_eth,input=>pre_random_out,q=>pre_mux_out);
	xadd_packet_header: add_packet_header PORT MAP (clock=>clock_eth,start=>start,N=>N,q=>header_out);
	xmux21: mux21 PORT MAP (in0=>header_out,in1=>pre_mux_out,sel=>mux_select,q_m=>random_out);
	xcounter_8: counter_8 PORT MAP (clock=>clock_eth, clear=>(NOT enable), count=>(start AND (NOT mux_select)), q=>counter_out);
	xsimple_comparator_8: simple_comparator_8 PORT MAP (in0=>counter_out,q=>mux_select);
	
END struct;